The present invention relates, in general, to testing of digital circuits, and more particularly to minimization of test patterns used to detect faults in digital circuits.
When undertaking test pattern generation and fault simulation, the number of faults that must be considered is typically smaller than the number of faults in the fault list. For stuck-at faults, the number of faults to be considered is typically reduced by using the concept of fault equivalence. Two faults are equivalent if all of the input vectors that can detect one of the faults can also detect the other. Using this idea, the number of faults that must be considered can be drastically reduced before the test generation process begins. This approach works well for stuck-at faults since such relationships between stuck-at faults are easy to derive and do not change with applied test vectors. Unfortunately, these relationships are quite difficult to derive for bridging faults.
There is a need for a method to reduce the number of faults which must be considered when generating test vectors to test for bridging faults. The method must be simple, easy to use, and must not require excessive computer time. Ideally, the method should take advantage of information that is already derived for other uses thus requiring very little extra overhead to implement.